Project

Current Status

Key Technologies of Ferroelectric Devices for Sub-Nanometer Nodes: Ferroelectric-Antiferroelectric Materials and Physics, Low-Power Memories and Computation with Energy Efficiency

Team Members

PI

Prof. Pin Su, Professor

Institute of Electronics, National Yang Ming Chiao Tung University

Prof. Jyun-Rong Su, Associate Professor

Dpt. Electrophysics, National Yang Ming Chiao Tung University

Prof. Min-Hung Lee, Professor

Program for Semiconductor Devices, Materials, and Hetero-integration, National Taiwan University

Prof. Ying-Tsang Tang, Assistant Professor

Dept. Electrical Engineering, National Central University

Prof. Po-Tsang Huang, Associate Professor

International College of Semiconductor Technology,
National Yang Ming Chiao Tung University

Introduction

Facing the grand challenges in density and energy efficiency of GAME (Gate，Architecture，Memory，ultralow-Energy device), sub-nanometer-node semiconductor technologies have to (1) be process-compatible with advanced CMOS, (2) be low-voltage and low-power, and (3) facilitate data-centric computing to break through the memory-wall bottleneck. This project addresses these requirements with key technologies regarding HfO₂-based CMOS-compatible ferroelectric devices to enable future low-power memories and in-memory computing with energy efficiency. In sub-project 1, ferroelectric FETs with high-density potential and multi-bit capability will be developed. Sub-project 2 will be devoted to advanced ferroelectric engineering and access scheme for future low-power and high-density memory applications. Using first-principle calculation, sub-project 3 will investigate ferroelectric/antiferroelectric super capacitor with angstrom-laminance. Sub-project 4 is regarding model development of ferroelectric/antiferroelectric devices for future memory applications. In sub-project 5, circuit design for energy-efficient in-memory computing using ferroelectric FETs will be carried out. With the five sub-projects, we aim at achieving the need for sub-nanometer-node device/chip technologies.

Structure of the project

Phase I: Achievements

Anti-ferroelectric Technology and Operation

Anti-ferroelectric (AFE) capacitors exhibit independent polarities on fatigue and leakage current for unipolar operation. In this work, opposite polarity cycling recovery (OPCR) with alternate polarity cycling is proposed for the first time to restore a fatigued polarization and leakage current back to its initial state, which involves the oxygen vacancy redistribution by opposite polarity cycling. Furthermore, AFE capacitor with OPCR demonstrates 50 periods and accumulation to 1×10¹² switching cycles. This result exhibits the nondegradation and complete restoration of P_r, as shown in Fig. 1. The proposed access scheme paves the way for AFE-based eDRAM applications. The relevant research results have been published in the 2022 International Electron Devices Meeting (IEDM 32.5) and invited for publication in IEEE Transactions on Electron Devices (T-ED).

Fig. 1. (a) Opposite polarity cycling recovery (OPCR) of alternate polarity cycling sequences. (b) The AFE capacitor with OPCR for 50 periods with alternate polarity and accumulates to 1×10¹² switching cycles.

Superlattice Deposition Technology with High Ferroelectric Phase HZO

This work adopts the superlattice (SL) ferroelectric oxide deposition method to enhance the ferroelectric phase ratio. This SL deposition technology is utilized for the double-layer ferroelectric structure to improve the stability of multi-level memory, as shown in Fig. 2. Compared to the traditional solid-solution (SS)-HZO, SL-HZO not only reduces the operating voltage (V_PG/ER=4V) but also exhibits ultra-low error rate = 7.5×10^-16, high 10⁹ cycling for 2-bit endurance and stable data retention > 10⁴ s. In addition, the SL-HZO also improves device variation of device-to-device (D2D) with nanoscale 3D FET. The homogeneous and coherent film of ferroelectric layer is highly demanded for FeFET scaling with high-density and high-performance. The relevant research results have been published in the 2022 International Electron Devices Meeting (IEDM 36.6).

Fig. 2. (a) Schematic diagram of solid-solution (SS), superlattice (SL) for double-layer ferroelectric structure. (b) For 4-state memory operation, the stability of read error rate is improved for SL as compares to SS.

Key Modeling Technologies for Antiferroelectric (AFE) / Ferroelectric (FE:)

We have successfully developed a physical model capable of describing the switching dynamics and frequency response of AFE/FE HZO. Our research results have been presented at IEEE 2021 (Sec. 15.4).
We have conducted modeling and characterization for switching dynamics of fatigued AFE/FE HZO. We have modeled the domain pinning probability considering fatigue mechanisms mediated by oxygen vacancy and charge injection. Our research results have been presented at IEEE 2022 (Sec. 13.4).
Our developed models can be used for future AFE/FE memory design and applications.