Project
Team Members
Nanosheet extensions and beyond
PI
Co-PI
Beyond the 2nm technology nodes, the GAAFETs will replace the FinFETs. In order to make GAAFETs be used in the 1.4nm, 1nm, and beyond 1nm technology nodes, Sub-project 1 focuses on the nanosheet extensions, including highly stacked GeSi channels, high-k gate dielectrics, and GeSn/GeSi ultrathin body, to improve the GAA performance (large ION, small IOFF, and small SS). It is necessary to reduce footprint and VDD with the same ION to achieve the G and E targets. Beyond the nanosheets, Sub-project 1 focuses on the novel transistor structure, including TreeFET and CFET, to enhance the logic gate density to achieve the G target. In Sub-project 2, the atomic layer deposition (ALD) and atomic layer annealing (ALA) techniques are used to fabricate the gate stack with improved interface quality, high dielectrics, reliability, and leakage suppression. The high-quality gate stack will be integrated into the transistors in Sub-project 1 to enhance ION and to reduce SS. In the transistor stacking, Sub-project 1 fabricates the CFET, and Sub-project 3 focuses on the circuit design. As the transistor density increases, the power generation will make the temperature of the devices become higher. Therefore, developing a packaging system with better heat dissipation in Sub-project 4 are necessary for heat dissipation of the transistors in Sub-project 1
To further improve the performance of highly stacked GeSi channels, the 6 stacked GeSi nanowires without parasitic channel are demonstrated by optimizing the wet etching. The device has the SS of 80mV/dec and ION/IOFF of 1.5E5. The ION per stack of 120μA and ION per footprint of 4600μA/μm are achieved at VOV=VDS=0.5V among Ge/GeSi 3D nFETs. The results have been published in 2022 VLSI-TSA, and won the Best Student Paper Award. Increasing the number of stacked channels is needed to further enhance the transistor ION. The 10 stacked GeSi nanowires without parasitic channel are demonstrated with the ION per stack of 140μA (6500μA/μm), and the results have been published in 2022 SISC. The 16 stacked GeSi nanowires are demonstrated with the ION per stack of 190μA (9400μA/μm) by the co-optimization of CVD epitaxy and isotropic wet etching, and the results have been submitted to Nature communications engineering.
The systematic work to pursue high-κ dielectrics is presented by optimizing the [Zr] in HfxZryO2 in our work. The peak high κ value of 47 is achieved in Hf0.2Zr0.8O2. The high-κ Hf0.2Zr0.8O2 gate dielectric is integrated into the stacked Ge0.98Si0.02 nanowire nFETs. High ION = 67 μA per stack and ION per perimeter = 740 μA/μm at VOV = VDS = 0.5V are achieved with 450 oC PMA. The result of this work has been published on IEEE EDL, 2022.
The pFET and nFET are able to fold on each other vertically to reduce 50% of cell area ideally in complementary FETs (CFET), as a promising transistor architecture beyond stacked nanosheets. The CFET transistor structure with 3D transistor stacking can enable further cell height scaling and Moore’s law scaling for 0.5nm technology node and beyond. Furthermore, high mobility GeSi channel is used for both nFET and pFET in CFET structure, while the process without S/D selective epitaxial growth can achieve self-aligned CFETs by multiple P/N junction isolation to effectively reduce the leakage current to replace dielectric layer isolation. The post-metallization annealing (PMA) with the low thermal budget of 400oC improves the inverter characteristics such as switching threshold voltage and voltage gain. The VTC of the Ge0.75Si0.25 CFET with a maximum gain of 9.6V/V at VCC=1.2V is achieved after the 400oC PMA. The results of GeSi CFET have been published in 2022 IEEE International Electron Devices Meeting.
