Project
Team Members
Cryogenic CMOS / SRAM Technology and Modeling for High Performance Computing
PI
Co-PI
This project will focus on the core goals set by the Å-generation semiconductor project call-for-proposal to develop new types of ultra-high-density three-dimensional logic gate devices, with the potential to achieve one-nanometer-equivalent logic technology platform; to develop wafer-level high-performance channels that are superior to conventional silicon channel materials; to develop Å-scale material analysis technologies; to develop deep learning model for CFET to analyze chip performance; to simulate cryogenic CMOS / SRAM circuits. The collaborative development of these five sub-projects allows us to break through existing limitations to tackle the challenges of higher density, lower energy, and higher energy efficiency chip technologies beyond the five-nanometer node, and to promote the forward-looking devices and chip technology required by the next-generation semiconductor industry.
There are five sub-projects in this joint project, and the correlation between each sub-project is highlighted in the above figure, covering front-end material analysis, advanced semiconductor manufacturing, chip performance simulation and low-temperature measurement. Sub-project 1 will fabricate Å-generation emerging devices including L-FET and V-FET; sub-project 2 will fabricate heterogeneous CFET, extend three-layers structure and develop high-density/high-performance CFET-on-CFET transistor; sub-project three will develop multi-layer hetero-epitaxy process, epitaxial layer selective etching, and Å-scale material analysis; sub-project four will developed CFET deep learning modeling for circuit- and chip-level operation, power consumption and heat flow analysis; sub-project 5 will perform cryogenic characterization of advanced transistors manufactured by sub-projects 1 and 2, perform cryogenic compact model parameter extraction, and further analyze cryogenic circuit power and performance.
In 2022, we published the paper “Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size” in the IEDM conference. In addition to further increasing the number of channels through layer transfer, the back-end IGZO high-mobility transistor is used to stack the PG, PU, and PD of the static random access memory (SRAM) on the same structure. Compared with traditional planar SRAM and CFET SRAM structure, SRAM with this 3D heterogeneous structure can reduce the footprint to a greater extent. Among them, the SRAM with CFET structure has 4 NMOSs and 2 PMOSs, so that the CFET structure cannot reduce the footprint to a greater extent. Based on this feature, stacking PG, PU, and PD on the same structure can greatly reduce the footprint and greatly reduce the static power consumption of SRAM. Figure 1 is a schematic diagram of a 6T SRAM circuit design; Figure 2 is a top view of a single structure of a 3D heterogeneous SRAM; Figure 3 is a simulated 3D heterogeneous SRAM RSNM characteristic; Figure 4 is a comparison diagram of SRAM static power consumption.
Fig.1 schematic diagram of a 6T SRAM circuit design
Fig.2 Top view SEM image of a single structure of a 3D heterogeneous SRAM；Fig.3 simulated 3D heterogeneous SRAM RSNM characteristic；Fig.4 6T SRAM static power consumption
For the first time, our team proposed an L-shaped field effect transistor (LFET), combining a horizontal and vertical transistor. Compared with a complementary field effect transistor (CFET), the LFET has more Low energy consumption and higher operating frequency. LFET can reduce energy consumption by 32.5% at the same operating frequency and increase frequency by 35% at the same operating bias. In addition, because the channels are not vertically stacked in the L-shaped structure, it is easier to make work function metals and contact holes for n-type and p-type transistors than CFET. The LFET structure can achieve heterogeneous integration only through epitaxy and lower the difficulty of the manufacturing process compared with CFET. The research results also be presented at the 2022 International Electronic Devices Meeting (IEDM).
Yang, C-Y., et al. “First Demonstration of Heterogeneous L-shaped Field Effect Transistor (LFET) for Angstrom Technology Nodes.” 2022 International Electron Devices Meeting (IEDM). IEEE, 2022.
Fig.1 Comparison of advantages and process challenges of LFET and CFET. Fig.2 Comparison of the power-delay relationship between LFET and CFET structures in TCAD simulation.
Fig.3 Experimental results of LFET devices (a) Voltage transfer curves; (b) ID-VD of the p-type transistor; (c) ID-VD of the n-type transistor
The GeOI-FinFET devices were simulated with reference to the TSRI process parameters, where the Channel Length was set to 30nm, Spacer K value to 3.9, and Spacer width to 10nm. The simulations were conducted at three different temperatures: 200K, 150K, and 77K, while keeping Vdd fixed at 0.25V.
It was observed that as the temperature decreased, the subthreshold swing (SS) decreased from 46.6 (mV/dec) at 200K to 29.33 (mV/dec) at 77K (a 37% reduction). Additionally, the delay time (CV/I) decreased from 13.62ps to 1.67ps (an 87.7% reduction), and the propagation delay for the inverter also improved from 3.4639s to 0.8589s (a 75% improvement).
The Ge-Vertical FET devices were modeled with reference to the TSRI process parameters, where the Channel Length was set to 170nm, Channel Diameter to 20nm, and Gate Overlap to 500nm. The simulations were performed with the device operating at a fixed Vdd of 0.25V under different temperature conditions (200K, 150K, and 77K), and their electrical characteristics were analyzed.
As the temperature decreased from 200K to 77K, the following improvements were observed:
- Subthreshold Swing (SS) improved by 57% (from 42.76 mV/dec at 200K to 18.22 mV/dec at 77K).
- Delay time (CV/I) decreased by 84% (from 1530.02ps at 200K to 247.14ps at 77K).
